This invention relates in general to semiconductor packages and packaging techniques and in particular, to semiconductor packages suitable for housing high density integrated circuits ("ICs") having large input-output ("I/O") connection requirements, and high volume production methods for assemblying those packages.
Current methods for packaging high density ICs having large I/O connection requirements are generally unsuitable for volume manufacturing. For example, numerous methods are used for sealing a lid over a high density IC in a high-performance, plastic pin-grid-array ("HP-PPGA") package. One method attaches a ceramic or metal lid to a package body by utilizing an epoxy seal ring. After the lid, seal ring, and package body are carefully aligned and clamped together, the entire structure is then placed in an oven at 100.degree.-225.degree. C. for 30- 90 minutes, depending upon the epoxy used. In this method, outgassing of the epoxy during the curing period has been a major problem and consequently, a sealing dam is typically needed in the package to match the seal ring. Other methods include placing a ceramic or metal lid with a flange over the package body, and back filling the package with liquid epoxy to effect the sealing upon curing of the structure; placing a ceramic or metal lid with a flat flange inside a dam ring of the package body, and covering the flange with liquid epoxy to effect the sealing upon curing; and placing a lid on top of the package body with some adhesive material, placing the entire structure in a cavity mold, and transfer molding the enclosed structure with epoxy.
In addition to HP-PPGA packages, other techniques for packaging high density ICs having large I/O connection requirements include cavity quad-flat-pack packages, also known as "clam shell" packages. These packages are typically made of either metal or plastic, containing two halves. A lead frame is either attached to one of the package halves or molded into the other. The two halves are then brought together and "glued" together. The "glue" typically used for this purpose is a thermal set epoxy which requires a long curing period of 30-90 minutes, depending upon the epoxy used. In this method, outgassing of the epoxy during the curing period has been a major problem and consequently, a vent hole in one of the package halves is often needed. In addition, proper alignment of the two package halves and the lead frame sandwiched in between them, can pose additional manufacturing problems.
Automated manufacturing of both the HP-PPGA and "clam shell" type of packages is difficult, because both require an oven bake and long, 30 to 90 minute curing time for their thermal set epoxy sealing materials to set. Further, both types of packages also experience outgassing problems during the epoxy bake.
In addition to being generally unsuitable for volume manufacturing, current methods for packaging high density ICs having large I/O connection requirements are also generally unsuitable for disassembly and subsequent reassembly of the packages. Disassembly or "decapping" of plastic packages is frequently desired for failure analysis purposes. It is especially desirable where a significant set of common failures are detected that can be remedied by incorporating corrective actions in the manufacturing process. For example, "open" circuits on leads may be caused by bonding wires pulling away from their contact points on either the bond pads on the semiconductor die or attachment points on the package leads. In either case, better bonding techniques might be employed to correct the problem. Also, "short" circuits between leads may be caused by adjacent bonding wires touching. In such a case, re-layout of the bond pad patterns on the semiconductor die may eliminate the problem by spacing further apart, the bond pads corresponding to the two touching bonding wires.
Reassembly of a disassembled plastic package would also be desirable if the originally failed part could be reworked and made functional. Referring back to the previous examples, if the "open" leads can be corrected by rebonding the bonding wires to their attachment points, then the reworked part would be functional and reassembly of the reworked part would be desirable. Also, if the "short" circuits between leads can be corrected by simply spreading the touching bonding wires apart, then the reworked part would be functional and reassembly of the reworked part would be desirable.
In the past, the cost of disassembling, reworking and reassemblying failed parts when compared to the ultimate selling price of those parts, made such reworking activity commercially impractical. Today, however, such reworking activity is commercially practical in certain situations, and certain technology trends which are leading to costlier packaged parts, indicate that the number of such situations will grow in the future. Included among these trends, several of which are interrelated, are larger semiconductor die both in terms of physical size and number of transistors, increased number of input/output connections between the die and external package leads, more complex and expensive packaging techniques and materials, and increased usage of multichip modules to enhance circuit performance by combining multiple chips in one package to reduce transmission delay times between chips and to allow different portions of the circuit to be partitioned into different chips so that those portions can be fabricated by the optimal process technology suitable for the functional purpose of that portion of the circuit.